A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications

A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures

This work introduces an application mapping methodology and case study for multi-processor on-chip architectures. Starting from the description of an application in standard sequential code (e.g. in C), first the application is profiled, parallelized when possible, then its components are moved to hardware implementation when necessary to satisfy performance and power constraints. After mapping...

Supporting Per-processor Local-allocation BuffersUsing Multi-processor Restartable Critical Sections

One challenge for runtime systems like the JavaTM platform that depend on garbage collection is the ability to scale performance with the number of allocating threads. As the number of such threads grows, allocation of memory in the heap becomes a point of contention. To relieve this contention, many collectors allow threads to preallocate blocks of memory from the shared heap. These per-thread...

Design of a Fuzzy Controller Chip with New Structure, Supporting Rational-Powered Membership Functions

In this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. The maximum output delay for general fuzzy logic controllers (FLC) is about 86 ns corresponding to 11.63 MFLIPS (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 M...

Processor allocator for chip multiprocessors

Parameters of a On-Chip Network for Multi-Processor System-on-Chip Environments